package Vshift

import chisel3._
import chisel3.util._
import VShiftInstr._

class VShiftTop(sec: Int = 1) extends Module {
  val io = IO(new Bundle() {
    val inst = Input(UInt(WIDTH32.W))
    val srcData = Input(new SrcData())
    val dstData = Input(UInt(WIDTH64.W))

    val Vd_low    = Output(UInt(WIDTH64.W))
    val Vd_hig    = Output(UInt(WIDTH64.W))

//    val Vd2 = Output(UInt(WIDTH64.W))
    val FPSR_QC = Output(Bool())
    val hitNum = Output(UInt(62.W))
  })


  val vShiftDecoder = Module(new VShiftDecoder())
  val vShiftDataReady = Module(new VShiftDataReady(sec))
  val vShiftWb = Module(new VShiftWb(sec))

  vShiftDecoder.io.inst := io.inst
  io.hitNum := vShiftDecoder.io.hitNum

  vShiftDecoder.io.vcon <> vShiftDataReady.io.vcon
  vShiftDecoder.io.vdec <> vShiftDataReady.io.vdec
  vShiftDecoder.io.velem <> vShiftDataReady.io.velem

  vShiftDecoder.io.vcon <> vShiftWb.io.vcon
  vShiftDecoder.io.vdec <> vShiftWb.io.vdec
  vShiftDecoder.io.velem <> vShiftWb.io.velem

  vShiftWb.io.dstData <> vShiftDataReady.io.dstData

  vShiftDataReady.io.srcData := io.srcData
  vShiftDataReady.io.dstValue := io.dstData

  io.FPSR_QC := vShiftDataReady.io.sat

  io.Vd_low := vShiftWb.io.wbData.result_low
  io.Vd_hig := vShiftWb.io.wbData.result_hig

}


object VShiftTop_Gen extends App {
  println("Generating the adder hardware")
  emitVerilog(new VShiftTop(), Array("--target-dir", "generated/VShiftTop/"))
}
